MDC Publications

Cite MDC

Please, use the following reference if you use MDC in your scientific paper or if you want to cite it:

Sau, C., Fanni, T., Rubattu, C., Raffo, L., & Palumbo, F. (2021). The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design. Microprocessors and Microsystems, 80, 103326.

@article{sau2021multi,
  title={The Multi-Dataflow Composer tool: An open-source tool suite for optimized coarse-grain reconfigurable hardware accelerators and platform design},
  author={Sau, Carlo and Fanni, Tiziana and Rubattu, Claudio and Raffo, Luigi and Palumbo, Francesca},
  journal={Microprocessors and Microsystems},
  volume={80},
  pages={103326},
  year={2021},
  publisher={Elsevier}
}

Publications

Journal Publications

• Ratto, F., Mainez, A. P., Sau, C., et al., “An Automated Design Flow for Adaptive Neural Network Hardware Accelerators,” Journal of Signal Processing Systems, Volume 95, pp. 1091-1113, (2023).

• Valente, G., Fanni, T., Sau, C., et al., “A Composable Monitoring System for Heterogeneous Embedded Platforms,” ACM Transactions on Embedded Computing Systems (TECS), Volume 20, pp. 1-34, (2021).

• Ratto, F., Fanni, T., Raffo, L. et Sau, C., “Mutual impact between clock gating and high-level synthesis in reconfigurable hardware accelerators,” Electronics, Volume 3, Art. N. 73, (2021).

• Sau, C., Fanni, T., Rubattu, C., et al., “Feasibility Study and Porting of the Damped Least Square Algorithm on FPGA,” IEEE Access, Volume 8, pp. 175483-175500, (2020).

• Li, L., Sau, C., Fanni, T., et al., “An integrated hardware/software design methodology for signal processing systems,” Journal of Systems Architecture, Volume 93, pp. 1-19 (2019).

• Rubattu, C., Palumbo, F., Sau, C., et al., “Dataflow-Functional High-Level Synthesis for Coarse-Grained Reconfigurable Accelerators,” IEEE Embedded Systems Letters, Volume 11, pp. 68-72 (2019).

• Sau, C., Palumbo, F., Pelcat, M., et al., “Challenging the Best HEVC Fractional Pixel FPGA Interpolators With Reconfigurable and Multifrequency Approximate Computing,” IEEE Embedded Systems Letters, Volume 9, pp. 65-68 (2017).

• Fanni, T., Li, L., Viitanen, T., et al, “Hardware design methodology using lightweight dataflow and its integration with low power techniques,” Journal of Systems Architecture, Volume 78, pp. 15-29 (2017).

• Palumbo, F., Fanni, T., Sau, C. et al., “Power-Awarness in Coarse-Grained Reconfigurable Multi-Functional Architectures: a Dataflow Based Strategy,” Journal of Signal Processing Systems, Volume 87, pages81–106 (2017).

• Palumbo, F., Carta, N., Pani, D. et al., “ The multi-dataflow composer tool: generation of on-the-fly reconfigurable platforms,” Journal of Real-Time Image Processing, Volume 9, 233–249 (2014).

Conference Proceedings

• Ratto, F., Raffo, L., Palumbo, F., “A multithread AES accelerator for Cyber-Physical Systems,” 20th ACM International Conference on Computing Frontiers (CF ’23), May 9–11, 2023, Bologna, Italy.

• Fanni, T., Madronal, D., Rubattu, C., “Run-time Performance Monitoring of Heterogenous Hw/Sw Platforms Using PAPI,” 6th International Workshop on FPGAs for Software Programmers, Barcelona, Spain, 2019, pp. 1-10.

• Rodríguez, A., and Fanni, T., “DEMO: Multi-Grain Adaptivity in Cyber-Physical Systems,” 2018 30th International Conference on Microelectronics (ICM), Sousse, Tunisia, 2018, pp. 44-47.

• Fanni, T., Rogriguez, A., Sau, C., et al., “Multi-Grain Reconfiguration for Advanced Adaptivity in Cyber-Physical Systems,” 2018 International Conference on ReConFigurable Computing and FPGAs (ReConFig), Cancun, Mexico, 2018, pp. 1-8.

• Li, L., Fanni, T., Viitanen, T., et al., “Low power design methodology for signal processing systems using lightweight dataflow techniques, Rennes, France, 2016, pp. 82-89.

• Fanni, T., Sau, C., Meloni, P., et al., “Power and clock gating modelling in coarse-grained reconfigurable systems,” 13th ACM International Conference on Computing Frontiers (CF), Como, Italy, 2016, pp. 1-8.

• Fanni, T., Sau, C., Raffo, L., et Palumbo, F., “Automated power gating methodology for dataflow-based reconfigurable systems,” 12th ACM International Conference on Computing Frontiers (CF), Ischia, Italy, 2015, pp. 1-6.

• Sau, C., Raffo, L., Palumbo, F., et al., “Automated design flow for coarse-grained reconfigurable platforms: An RVC-CAL multi-standard decoder use-case,” 2014 International Conference on Embedded Computer Systems: Architectures, Modeling, and Simulation (SAMOS XIV), Agios Konstantinos, Greece, 2014, pp. 59-66.

• Palumbo, F., Carta, N., and Raffo, L., “The multi-dataflow composer tool: A runtime reconfigurable hdl platform composer,” Conference on Design and Architectures for Signal and Image Processing (DASIP), Tampere, Finland, 2011, pp. 1-8.

PhD Theses

• FANNI, Tiziana (2019). Power and Energy Management in Coarse-Grained Reconfigurable Systems: methodologies,automation and assessments. Thesis (Doctoral), D.R.I.E.I. (University of Cagliari).

• SAU, Carlo (2016). Dataflow Based Design Suite for the DEvelopment and Management of Multi-Functional Reconfigurable Systems. Thesis (Doctoral), D.R.I.E.I. (University of Cagliari).